A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology.

Chua-Chin Wang Wen-Je Lu Hsin-Yuan Tseng

Published in: ISCAS (2013)

Keyphrases

cmos technology
low power
high speed
power consumption
low cost
spl times
low voltage
real time
parallel processing
mixed signal
digital signal processing
object detection
clock frequency
silicon on insulator
power dissipation
neural network
pattern recognition
image sensor