Crossbar latch-based combinational and sequential logic for nano FPGA.
Tamer MohamedGraham A. JullienWael M. BadawyPublished in: NANOARCH (2007)
Keyphrases
- logic circuits
- low power
- asynchronous circuits
- gate array
- power reduction
- high speed
- low cost
- low power consumption
- single chip
- flip flops
- logic programming
- nano scale
- automated reasoning
- scheduling algorithm
- modal logic
- classical logic
- real time image processing
- power consumption
- hardware implementation
- field programmable gate array
- high density
- proof theory
- verilog hdl
- systolic array
- real time
- digital circuits
- hardware design
- computational properties
- multi valued
- response time
- knowledge representation