Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.
Abdessatar AbderrahmanBozena KaminskaYvon SavariaPublished in: EDAC-ETC-EUROASIC (1994)
Keyphrases
- power consumption
- logic circuits
- power dissipation
- low power
- tunnel diode
- delay insensitive
- chip design
- high speed
- analog vlsi
- circuit design
- asynchronous circuits
- vlsi circuits
- cmos technology
- power reduction
- estimation error
- energy dissipation
- noise reduction
- low voltage
- power management
- signal to noise ratio
- signal subspace
- parameter estimation
- image noise
- noise model
- noise level
- noisy data
- measurement error
- single chip
- power supply
- accurate estimation
- logic synthesis
- low cost