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A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Jong-Ru Guo
Chao You
Kuan Zhou
Michael Chu
Peter F. Curran
Jiedong Diao
Bryan S. Goda
Russell P. Kraft
John F. McDonald
Published in:
Integr. (2005)
Keyphrases
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high speed
low cost
real time
field programmable gate array
fpga device
pipelined architecture
neural network
signal processing
high frequency
hardware design
reconfigurable hardware
verilog hdl