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19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Fazil AhmadGreg UnruhAmrutha IyerPin-En SuSherif AbdallaBo ShenMark ChambersIchiro Fujimori
Published in: ISSCC (2016)
Keyphrases
  • power consumption
  • clock gating
  • low power
  • high speed
  • user interface
  • low cost
  • circuit design
  • cmos technology
  • power reduction
  • web applications
  • embedded systems
  • propositional logic
  • nm technology