A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle.
Sung-Rung HanShen-Iuan LiuPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- duty cycle
- clock frequency
- control loop
- power consumption
- control scheme
- closed loop
- control system
- high end
- control strategy
- concurrency control
- parallel computing
- parallel architecture
- field programmable gate array
- low power
- massively parallel
- cmos technology
- database systems
- fine granularity
- high speed
- real time
- parallel execution