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A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure.

Akira OhtaNorio HigashisakaTetsuya HeimaTakayuki HisakaHirofumi NakanoRyuji OhmuraTadashi TakagiNoriyuki Tanino
Published in: IEEE J. Solid State Circuits (1999)
Keyphrases
  • gate array
  • image processing
  • logic circuits
  • data sets
  • learning algorithm
  • pattern recognition
  • high resolution
  • high speed
  • parallel algorithm
  • reliability assessment