Two-stage channel routing for CMOS gate arrays.
J.-N. SongY.-K. ChenPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1988)
Keyphrases
- cmos technology
- focal plane
- multiple input
- field effect transistors
- high speed
- nm technology
- multi channel
- gate dielectrics
- routing problem
- metal oxide semiconductor
- division multiple access
- power consumption
- routing algorithm
- low cost
- analog vlsi
- multiple access
- infrared
- power supply
- routing protocol
- shortest path
- network topology
- liquid crystal displays
- low power
- integrated circuit
- network topologies
- wireless channels
- circuit design
- communication channels
- high density
- routing decisions