40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications.
Michael I. FullerJames P. MabryJohn A. HossackTravis N. BlalockPublished in: ACM Great Lakes Symposium on VLSI (2003)
Keyphrases
- mixed signal
- cmos technology
- low power
- low voltage
- high speed
- vlsi circuits
- random access memory
- dynamic random access memory
- analog to digital converter
- embedded dram
- power consumption
- low cost
- multi channel
- parallel processing
- embedded systems
- flip flops
- power dissipation
- high density
- real time
- frame rate
- input output