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ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.

Kun-Hsien LinMing-Dou Ker
Published in: ISCAS (2) (2005)
Keyphrases
  • cmos technology
  • low power
  • power dissipation
  • spl times
  • low voltage
  • user interface
  • image analysis
  • design process
  • case study
  • input output
  • main memory
  • single chip