A Leakage-Compensated PLL in 65-nm CMOS Technology.

Chao-Ching Hung Shen-Iuan Liu

Published in: IEEE Trans. Circuits Syst. II Express Briefs (2009)

Keyphrases

cmos technology
low power
low voltage
leakage current
power consumption
spl times
parallel processing
silicon on insulator
low cost
power dissipation
image sensor
high speed
mixed signal
digital signal processing
dynamic range
stereo images
computer vision