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A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects.
Daniël Schinkel
Eisse Mensink
Eric A. M. Klumperink
Ed J. M. van Tuijl
Bram Nauta
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
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high speed
low cost
input output
phase locked loop
cmos technology
computer simulation
fiber optic
wireless sensor networks
image registration
high density
global information
power dissipation
average error
chip design