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Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
Ming Ling
Xiaojing Shang
Shan Shen
Tianxiang Shao
Jun Yang
Published in:
IEEE Access (2019)
Keyphrases
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low voltage
random access memory
access latency
leakage current
design considerations
power management
power line
prefetching
sensor networks
cmos technology
power consumption
signal processing
computer systems
cloud computing