Login / Signup
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator.
Ryota Sekimoto
Akira Shikata
Tadahiro Kuroda
Hiroki Ishikuro
Published in:
ESSCIRC (2011)
Keyphrases
</>
low voltage
cmos technology
high speed
low power
power consumption
leakage current
power line
power management
asynchronous circuits
synthetic aperture radar
design considerations
sar images
parallel processing
random access memory
power dissipation
energy efficiency
real time
mixed signal
learning styles
low cost