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A High Performance Router Architecture for Interconnection Networks.
José Duato
Pedro López
Federico Silla
Sudhakar Yalamanchili
Published in:
ICPP, Vol. 1 (1996)
Keyphrases
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interconnection networks
network on chip
parallel computers
fault tolerant
message passing
routing algorithm
multistage
real time
bayesian networks
signal processing
parallel algorithm
packet switching