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A High Performance Router Architecture for Interconnection Networks.

José DuatoPedro LópezFederico SillaSudhakar Yalamanchili
Published in: ICPP, Vol. 1 (1996)
Keyphrases
  • interconnection networks
  • network on chip
  • parallel computers
  • fault tolerant
  • message passing
  • routing algorithm
  • multistage
  • real time
  • bayesian networks
  • signal processing
  • parallel algorithm
  • packet switching