A Reconfigurable Processor for Phylogenetic Inference.
Pei LiuAhmed HemaniKolin PaulPublished in: VLSI Design (2011)
Keyphrases
- systolic array
- digital signal
- functional units
- reconfigurable architecture
- high speed
- parallel processing
- computation intensive
- functional verification
- general purpose
- data flow
- computer architecture
- hardware implementation
- low cost
- parallel architecture
- multi objective evolutionary
- parallel processors
- level parallelism
- instruction set
- single processor
- memory management
- processing elements
- parallel architectures
- neural network
- single chip
- high end
- distributed memory
- parallel implementation
- information systems
- learning algorithm