TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache.
Adarsh PatilPublished in: CoRR (2020)
Keyphrases
- main memory
- memory hierarchy
- cache misses
- memory subsystem
- memory management
- dynamic random access memory
- data structure
- computing power
- virtual memory
- database management systems
- index structure
- external memory
- memory access
- prefetching
- flash memory
- high density
- computer systems
- multicore processors
- parallel architectures
- cloud computing
- multi core processors
- general purpose
- caching scheme
- query processing
- database