Optimizing SDRAM bandwidth for custom FPGA loop accelerators.
Samuel BaylissGeorge A. ConstantinidesPublished in: FPGA (2012)
Keyphrases
- field programmable gate array
- single chip
- hardware implementation
- parallel computing
- embedded systems
- high speed
- domain specific
- computing systems
- image processing algorithms
- software implementation
- low cost
- hardware design
- video streaming
- network bandwidth
- real time image processing
- hardware architecture
- low power
- real time
- fpga implementation
- bandwidth allocation
- bandwidth utilization
- fpga technology
- image processing
- image sensor
- application specific
- dedicated hardware
- clock frequency
- fpga device
- signal processing