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Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS.

Jian LiuXin WangHui ZhaoQiang FangAlbert Z. WangLin LinHe TangSiqiang FanBin ZhaoShi-Jie WenRichard Wong
Published in: IEEE J. Solid State Circuits (2011)
Keyphrases
  • low voltage
  • image processing
  • circuit design
  • case study
  • high resolution
  • digital images
  • high speed
  • design process
  • design considerations
  • cmos technology