A low voltage second order biquad using pseudo floating-gate transistors.

Øivind Næss Espen A. Olsen Yngvar Berg Tor Sverre Lande

Published in: ISCAS (1) (2003)

Keyphrases

floating gate
low voltage
cmos technology
power line
design considerations
higher order
power management
circuit design
low power
response time
power consumption
leakage current