Physical-aware system-level design for tiled hierarchical chip multiprocessors.

Jordi Cortadella Javier de San Pedro Nikita Nikitin Jordi Petit

Published in: ISPD (2013)

Keyphrases

low cost
case study
high speed
hierarchical structure
computer aided
design methodology
single chip
functional verification
information systems
high resolution
design process
design considerations
circuit design
vlsi implementation