Hardware Optimized Approximate Adder with Normal Error Distribution.
Raunaq NayarPadmanabhan BalasubramanianDouglas L. MaskellPublished in: ISVLSI (2020)
Keyphrases
- error detection
- low cost
- hardware and software
- error rate
- real time
- computing power
- spatial distribution
- hardware implementation
- vlsi implementation
- probability distribution
- error analysis
- random variables
- computing systems
- data flow
- relative error
- error propagation
- error correction
- expected error
- parallel hardware
- central processor
- exact solution
- personal computer
- error bounds
- graphical models
- general purpose
- least squares
- upper bound
- image processing