A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects.
Joonsung BaeJoo-Young KimHoi-Jun YooPublished in: ISCAS (2008)
Keyphrases
- cmos technology
- ultra low power
- power dissipation
- high speed
- low power
- power consumption
- analog vlsi
- clock frequency
- low voltage
- chip design
- low cost
- nm technology
- parallel processing
- circuit design
- image sensor
- single chip
- cmos image sensor
- mixed signal
- phase locked loop
- average error
- rms error
- digital signal processing
- input output
- frequency response
- focal plane
- delay insensitive
- physical design
- finite state machines
- data acquisition
- silicon on insulator
- signal processing