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Architecture and implementation of a highly parallel single-chip video DSP.
Hironori Yamauchi
Yutaka Tashiro
Toshihiro Minami
Yutaka Suzuki
Published in:
IEEE Trans. Circuits Syst. Video Technol. (1992)
Keyphrases
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highly parallel
single chip
low power
efficient implementation
low cost
real time
computing systems
high speed
video data
parallel architectures
general purpose
video sequences
parallel programming
multimedia
high frequency
edge detection
high resolution
image sensor
image sequences