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A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.

Taejoong SongHoonki KimWoojin RimHakchul JungChangnam ParkInhak LeeSanghoon BaekJonghoon Jung
Published in: IEEE J. Solid State Circuits (2022)
Keyphrases
  • power consumption
  • cmos technology
  • high speed
  • low power
  • nm technology
  • case study
  • adaptive learning
  • mathematical analysis
  • power reduction
  • leakage current