A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS.
Guiqiang PengLeibo LiuSheng ZhouShouyi YinShaojun WeiPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
- parallel processing
- cmos technology
- xilinx virtex
- clock frequency
- circuit design
- channel estimation
- hardware architecture
- fading channels
- hardware implementation
- embedded dram
- multipath
- silicon on insulator
- communication systems
- ofdm system
- low power
- design methodology
- application specific
- mimo systems
- cdma systems
- high speed
- bit error rate
- single chip
- power consumption
- edge detection
- low cost