Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.

Francisco J. Villa Manuel E. Acacio José M. García

Published in: HPCC (2005)

Keyphrases

memory subsystem
multiprocessor architecture
production system
ibm zenterprise
instruction set
input output
dynamic random access memory
high speed
real time
image quality
image sequences
management system
image compression
video decoder