FPGA PUF using programmable delay lines.
Mehrdad MajzoobiFarinaz KoushanfarSrinivas DevadasPublished in: WIFS (2010)
Keyphrases
- single chip
- low cost
- electronic devices
- digital signal processors
- field programmable gate array
- straight line
- hardware implementation
- programmable logic
- real time image processing
- hough transform
- real time
- high speed
- line segments
- general purpose
- critical path
- general purpose processors
- low power
- line drawings
- signal processor
- signal processing
- hardware architecture
- low power consumption
- processor array
- systolic array
- verilog hdl
- digital signal
- reconfigurable hardware
- dedicated hardware
- hardware design
- computing systems
- image processing