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Dynamic clock synchronization scheme between voltage domains in multi-core architecture.

Jaehyun KimKiyoung ChoiSang-Heon LeeSoojung Ryu
Published in: VLSI-SoC (2016)
Keyphrases
  • multi core architecture
  • duty cycle
  • high speed
  • power system
  • chaotic systems
  • general purpose
  • resource management
  • energy efficient