High performance code compression architecture for the embedded ARM/THUMB processor.
X. H. XuC. T. ClarkeS. R. JonesPublished in: Conf. Computing Frontiers (2004)
Keyphrases
- embedded processors
- industry standard
- computation intensive
- instruction set
- single chip
- management system
- parallel architecture
- multi processor
- distributed memory
- embedded systems
- data flow
- image compression
- embedded dram
- high speed
- real time
- code generation
- dynamic random access memory
- compression ratio
- processor core
- parallel implementation
- compression scheme
- instruction set architecture
- single processor
- embedded image
- parallel processing
- error detection
- data compression
- source code