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Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.

Shankarram AthreyaHiva HedayatiShayan KazemkhaniYanfei ChenSaurabh VatsMichael D. ScottBart ZeydelPeter KellerJian WangBhaskarareddy AvulaBoris MurmannEchere Iroaga
Published in: ESSCIRC (2018)
Keyphrases
  • high speed
  • camera calibration
  • detection algorithm
  • power consumption
  • aspect ratio
  • hand eye coordination
  • duty cycle