Verification work reduction methodology in low-power chip implementation.
Masanori KurimotoTakeshi YamamotoSatoshi NakanoAtsuto HanamiHiroyuki KondoPublished in: ACM Trans. Design Autom. Electr. Syst. (2012)
Keyphrases
- low power
- cmos technology
- low cost
- high speed
- signal processor
- single chip
- ultra low power
- power consumption
- mixed signal
- low power consumption
- vlsi architecture
- power reduction
- power dissipation
- vlsi circuits
- nm technology
- image sensor
- model checking
- logic circuits
- high power
- design methodology
- wireless transmission
- low voltage
- functional verification
- digital signal processing
- real time
- signal processing
- hardware and software
- gate array