Power estimation for large sequential circuits.

Joseph N. Kozhaya Farid N. Najm

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2001)

Keyphrases

power consumption
estimation algorithm
neural network
high speed
parametric models
parameter estimation
low power
power reduction
information systems
image registration
maximum likelihood estimation
estimation process
circuit design
power dissipation
delay insensitive
chip design