A 145µW 8×8 parallel multiplier based on optimized bypassing architecture.
Sunjoo HongTaehwan RohHoi-Jun YooPublished in: ISCAS (2011)
Keyphrases
- multi processor
- management system
- parallel architecture
- hardware implementation
- master slave
- knowledge base
- parallel processing
- real time
- distributed processing
- parallel implementation
- processing elements
- architectural design
- website
- artificial intelligence
- neural network
- interior point methods
- floating point
- shared memory