Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS.
Jiyoung LeeYoungmin KimPublished in: ISOCC (2022)
Keyphrases
- cmos technology
- power consumption
- low power
- nm technology
- low voltage
- silicon on insulator
- power reduction
- high speed
- power dissipation
- analog vlsi
- metal oxide semiconductor
- disk drives
- circuit design
- leakage current
- read write
- parallel processing
- power saving
- random access memory
- low cost
- image sensor
- delay insensitive
- power management
- mixed signal
- noise level
- write operations
- human computer interaction
- embedded dram
- dynamic random access memory
- digital signal processing
- signal to noise ratio
- noisy data
- vlsi circuits
- analog circuits
- wide dynamic range
- noise reduction
- real time