A novel architecture of local memory for programmable SIMD vision chip.
Zhe ChenJie YangCong ShiNanjian WuPublished in: ASICON (2013)
Keyphrases
- processor array
- digital signal processors
- single instruction multiple data
- memory access
- low cost
- level parallelism
- parallel algorithm
- single chip
- real time
- signal processor
- memory subsystem
- parallel computers
- multithreading
- computer vision
- analog vlsi
- vlsi implementation
- high speed
- processing elements
- parallel processing
- low power
- memory management
- smart camera
- vision system
- mesh connected
- associative memory
- memory requirements
- nm technology
- parallel implementation
- massively parallel
- management system
- signal processing
- host computer
- memory bandwidth
- programmable logic
- array processor
- design methodology
- embedded systems
- cmos technology
- image processing
- data access
- high density