Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology.
Ming-Dou KerWei-Jen ChangPublished in: Microelectron. Reliab. (2007)
Keyphrases
- low voltage
- cmos technology
- power consumption
- power dissipation
- low power
- high voltage
- design considerations
- high speed
- leakage current
- parallel processing
- mixed signal
- power management
- random access memory
- energy efficiency
- reactive power
- digital signal processing
- real time
- data center
- low cost
- ibm power processor
- silicon on insulator
- operating conditions
- design methodology
- user interface
- neural network