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Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology.
Hung-Chang Yu
Kai-Chun Lin
Ku-Feng Lin
Chin-Yi Huang
Yu-Der Chih
Tong-Chern Ong
Tsung-Yung Jonathan Chang
Sreedhar Natarajan
Luan C. Tran
Published in:
ISSCC (2013)
Keyphrases
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optimization scheme
nm technology
power consumption
design considerations
low power
random access memory
times faster
power dissipation
simplex method
low cost
location prediction
high speed
image processing
user interface
macroblock