A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism.
Marc de KruijfShuou NomuraKarthikeyan SankaralingamPublished in: DSN (2010)
Keyphrases
- unified model
- case study
- cmos technology
- engineering design
- design process
- cmos image sensor
- design requirements
- participatory design
- single chip
- circuit design
- low power
- cost effective
- data processing
- human factors
- current status
- power consumption
- power supply
- interaction design
- knowledge based systems
- user interface
- active participation
- information systems