Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing.

Hervé J. Touati Hamid Savoj Robert K. Brayton

Published in: ICCAD (1991)

Keyphrases

logic circuits
low power
power dissipation
clustering algorithm
clustering method
gate array
k means
functional decomposition
power consumption
tunnel diode
low cost
logic synthesis
digital signal processing
high speed
computer vision
neural network
parallel processing
real time
anomaly detection