A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.
Suhas ShivapakashHardik JainOlaf HellwichFriedel GerfersPublished in: ISCAS (2020)
Keyphrases
- neural network
- pattern recognition
- auto associative
- computational cost
- fuzzy logic
- power consumption
- highly efficient
- associative memory
- neural network model
- computer architecture
- memory usage
- computational power
- parallel implementation
- efficient implementation
- memory requirements
- main memory
- fault diagnosis
- artificial neural networks
- learning algorithm
- machine learning