A PWL ladder circuit which exhibits hysteresis.
Mauro ParodiMarco StoraceSilvano CincottiPublished in: Int. J. Circuit Theory Appl. (1994)
Keyphrases
- high speed
- circuit design
- electronic circuits
- analog circuits
- analog vlsi
- artificial intelligence
- highly nonlinear
- digital circuits
- duty cycle
- artificial neural networks
- multi agent
- series parallel
- information systems
- frequency response
- genetic algorithm
- delay insensitive
- logic synthesis
- neural network
- shift register
- database