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Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier.
Koken Chin
Hao San
Atsushi Kitajima
Yoshiaki Arai
Jun Yamashita
Hisashi Ito
Published in:
ISPACS (2016)
Keyphrases
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low voltage
leakage current
cmos technology
circuit design
power line
high speed
design considerations
analog vlsi
delay insensitive
high sensitivity
information security
low power
power management
dynamic range
real time
low cost
power consumption
critical infrastructure
energy consumption
vlsi circuits