Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking.
Hongce ZhangAarti GuptaSharad MalikPublished in: VMCAI (2021)
Keyphrases
- model checking
- temporal logic
- model checker
- formal specification
- formal verification
- finite state
- automated verification
- temporal properties
- reachability analysis
- bounded model checking
- pspace complete
- finite state machines
- computation tree logic
- timed automata
- verification method
- concurrent systems
- partial order reduction
- transition systems
- process algebra
- symbolic model checking
- epistemic logic
- formal methods
- asynchronous circuits
- deterministic finite automaton
- modal logic
- reactive systems
- satisfiability problem
- multi agent systems