A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.
Suhas ShivapakashHardik JainOlaf HellwichFriedel GerfersPublished in: IEEE Open J. Circuits Syst. (2021)
Keyphrases
- neural network
- memory requirements
- memory usage
- compute intensive
- computational power
- auto associative
- multi layer perceptron
- data sets
- computational cost
- associative memory
- random access memory
- neural nets
- neural network model
- fault diagnosis
- artificial neural networks
- data mining
- multilayer perceptron
- feed forward
- high efficiency
- power consumption
- activation function
- self organizing maps
- limited memory
- bit wise