Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache.

Minwoo Jang Seungkyu Lee Jaeha Kung Daehoon Kim

Published in: IEEE Access (2020)

Keyphrases

dynamic random access memory
main memory
memory subsystem
hit rate
back end
data access
prefetching
query processing
cache management
cache misses
caching scheme
data structure
index structure
high density
memory access
database management systems
data model
embedded processors
shared memory multiprocessors