A novel architecture for on-chip path delay measurement.
Xiaoxiao WangMohammad TehranipoorRamyanshu DattaPublished in: ITC (2009)
Keyphrases
- vlsi implementation
- host computer
- analog vlsi
- management system
- software architecture
- destination node
- level parallelism
- design considerations
- path length
- neural network
- optimal path
- high density
- shortest path
- low cost
- physical design
- power dissipation
- data flow
- functional units
- hardware implementation
- real time
- cmos image sensor