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An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.

Yi ShenJunyan HaoShubin LiuZeshuai AnDengquan LiRuixue DingZhangming Zhu
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2023)
Keyphrases
  • post processing
  • embedded systems
  • real time
  • sar images
  • synthetic aperture radar
  • learning environment
  • digital images