PACE: Processor Architectures for Circuit Emulation.

Reiner Kolla Oliver Springauf

Published in: IPPS/SPDP Workshops (1998)

Keyphrases

high speed
memory management
parallel architectures
multi core processors
gate array
low power
parallel processing
operating system
electronic circuits
single chip
single processor
multicore processors
real time
chip design
duty cycle
delay insensitive
logic synthesis
single instruction multiple data