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Yue Niu
Publication Activity (10 Years)
Years Active: 2016-2023
Publications (10 Years): 8
Top Topics
Cosine Transform
Xilinx Virtex
Fpga Implementation
Compression Algorithm
Top Venues
CoRR
GlobalSIP
PCM (1)
FPGA
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Publications
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Yue Niu
,
Rajgopal Kannan
,
Ajitesh Srivastava
,
Viktor K. Prasanna
Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration.
CoRR
(2023)
Yue Niu
,
Rajgopal Kannan
,
Ajitesh Srivastava
,
Viktor K. Prasanna
Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration.
FPGA
(2020)
Yue Niu
,
Hanqing Zeng
,
Ajitesh Srivastava
,
Kartik Lakhotia
,
Rajgopal Kannan
,
Yanzhi Wang
,
Viktor K. Prasanna
SPEC2: SPECtral SParsE CNN Accelerator on FPGAs.
HiPC
(2019)
Yue Niu
,
Hanqing Zeng
,
Ajitesh Srivastava
,
Kartik Lakhotia
,
Rajgopal Kannan
,
Yanzhi Wang
,
Viktor K. Prasanna
SPEC2: SPECtral SParsE CNN Accelerator on FPGAs.
CoRR
(2019)
Wei Zhou
,
Yue Niu
,
Guanwen Zhang
Sensitivity-Oriented Layer-Wise Acceleration and Compression for Convolutional Neural Network.
IEEE Access
7 (2019)
Yue Niu
,
Zhenyu Liu
,
Chunsheng Mei
,
Xiangyang Ji
,
Wei Zhou
,
Dongsheng Wang
Sensitivity-based acceleration and compression algorithm for convolution neural network.
GlobalSIP
(2017)
Chunsheng Mei
,
Zhenyu Liu
,
Yue Niu
,
Xiangyang Ji
,
Wei Zhou
,
Dongsheng Wang
A 200MHZ 202.4GFLOPS@10.8W VGG16 accelerator in Xilinx VX690T.
GlobalSIP
(2017)
Wei Zhou
,
Yue Niu
,
Xiaocong Lian
,
Xin Zhou
,
Jiamin Yang
A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC.
PCM (1)
(2016)